Cacheminne

The average memory access time for a processor developed by Tyrell Corporation with 1 level of cache is2.4 clock cycles. The properties of the memory system are as follows:

• If data is present in the cache and is valid, it can be accessed in 1 clock cycle.
• If data is not found in the cache, 80 clock cycles are needed to get it from the memory.

As a designer who works for Tyrell Co. you are given the task of improving average memory access times by65%. To achieve that goal you are considering adding a 2nd level of cache. This new cache has the followingproperties:

• The new L2 cache can be accessed in 6 clock cycles.
• The addition of this new cache does not affect the L1 cache’s access patterns or hit times.
• Accessing the main memory would still require 80 additional clock cycles.

To obtain the desired improvement and keep your boss happy, how often must data be found in L2 cache?(in other words, what should be the hit-rate of L2 cache?)

Here is my solution:

Let primary cpu = A and secondary cpu= B;

Speed-up = AMAT(A) / AMAT (B) --> AMAT (B) = (1-0.65) *AMAT(A) = 0.35 * 2.4 = 0.84 clock cycles.

For calculating the hit rate of L2 cache, we know hit rate = 1 - miss rate. The miss rate for L2 can be derived from the following formula:

AMAT(B)= hit time (L1) + miss rate (L1) * (hit time (L2) + miss rate(L2) * (miss penalty (L2)))    ##

But first we need to calculate the miss rate (L1) by the following formula:

AMAT(A)= hit time (L1) + miss rate (L1) * (miss penalty (L1))2.4 = 1 + miss rate (L1) * 80miss rate (L1) = 0.0175

Now, we place this value into ##:

(Let miss rate (L2) = X)

0.84 = 1 + 0.0175 ( 6 + X * 80)X = - 0.19

This value should not be negative!! What is wrong with this solution?